WUS (unsafe) detection (kick back sensing)

ABSTRACT

An unsafe detection circuit for detecting a kickback signal including an input circuit for inputting a kickback signal, a circuit for detecting the presence or absence of said kickback signal, and a fault detection circuit to respond to said presence or absence of said kickback signal to provide an indication of a fault.

FIELD OF THE INVENTION

[0001] This invention relates in general to the field of mass storagedevices and more particularly to a pre-amplifier and a device fordetermining faults in a head.

BACKGROUND OF THE INVENTION

[0002] A hard disk drive includes a stack of magnetically coded plattersthat are used for storing information. The magnetically coded plattersare mounted together in a stacked position through a spindle which maybe referred to as a platter stack. The platter stack is typicallyrotated by a motor that is referred to generally as a spindle motor or aservo motor. A space is provided between each platter to allow aread/write head or slider to be positioned on each side of the platterso that information may be stored and retrieved. Information is storedon each side of each platter and is generally organized into sectortrack zones and cylinders. Each of the read/write heads or sliders ismounted into one end of the dedicated suspension arm so that each of theread/write heads may be positioned as desired. The opposite end of eachof the suspensions arms is coupled together at the voice coil motor toform one unit or assembly that is positionable by a voice coil motor.Each of the suspensions arms is provided in a fixed position relative toeach other. The voice coil motor positions all of the suspensions armsso that the read/write head is properly positioned for reading orwriting information. The read/write heads or sliders may move from atleast one inner diameter to an outer diameter where data is stored. Thisdistance may be referred to as a data stroke.

[0003] Hard disk drives also include a variety of electronic circuitryfor processing data input for controlling its overall operation. Theelectronic circuitry may include a pre-amplifier, a read channel, awrite channel, a servo controller, a motor control circuit, a read onlymemory open (ROM), a random access memory (RAM) and variety of diskcontrol circuitry to control the operation of the hard disk drive and toproperly interface the hard disk drive to the system bus. Thepre-amplifier may contain a read pre-amplifier and a write pre-amplifierthat is also referred to as a write driver. The pre-amplifier may beimplemented in a single integrated circuit or may be a separateintegrated circuit such as read pre-amplifier, a write pre-amplifier, ora write driver. The disk control circuitry generally includes a separatemicroprocessor for executing instructions stored in memory to controlthe operation and interface of the hard disk drive. The hard disk driveperforms read, write and servo operations when storing and retrievingdata. The write operation includes retrieving data from a system bus andstoring to data in the RAM. The microprocessor schedules a series ofevents to allow the information to be transferred from the ROM toplatters through the write channel. Before the information istransferred, the read and write heads are positioned on the appropriatetrack, and the appropriate sector of the track is located. The data fromthe RAM is then communicated to the write channel as a digital writesignal. The write channel processes the digital write signal andgenerates an analog write signal. In doing this, the write channel mayencode the data so that the data can be more reliably retrieved later.The digital write signal may then be provided to an appropriateread/write head after first being amplified by the pre-amplifier. Inread operation, the appropriate sector is read, is located and data thathas previously written to the platter is read. The appropriateread/write head senses the changes in the magnetic flux and generates acorresponding analog read signal. The analog read signal is providedback to the electronic circuitry where the pre-amplifier amplifies theanalog read signal. The amplified analog read signal is then provided tothe read channel where the read channel conditions the signals anddetects “zeros” and “ones” from the signal to generate a digital readsignal. The read channel may condition the signal by amplifying thesignal to an appropriate level using automatic gain control (AGC)technique. The read channel may then filter the signal to eliminateunwanted high noise, equalize the channel, detect “zeros” and “ones”from the signal and format the digital read signal. The digital readsignal is then transferred from the read channel and stored in the RAM.The microprocessor may then communicate to the host that data is readyto be transferred. The read channel may be implemented using any of avariety of known or available channels. For example, the read channelmay be implemented as a peak detection type read channel or as a moreadvanced type of read channel utilizing discreet time signal processing.The peak detection read channel involves level detecting the amplifiedanalog read signal and determines if the wave form level is above athreshold level during a sampling window. The discreet time signalprocessing type read channel synchronously samples the amplified readsignal using a data recovery clock. The sample is then processed througha series of mathematical manipulations using signal processing theory togenerate the digital read signal. There are several types of discreettime signal processing read channels such as partial response, maximumlikelihood (PRML) channel and extended PRML channel or enhanced extendedPRML channel, a fixed delay tree search channel and a decision feedbackequalization channel.

[0004] As the disk platters are moving, the read write heads must alignor stay on a particular track. This is accomplished by the servooperations through use of the servo controller provided in a servocontrol loop. In servo operation, a servo wedge is read from the trackthat generally includes track identification information and trackmisregistration information. The track misregistration information mayalso be referred to as position error information. The position errorinformation may be provided as servo bursts that may be used during readand write operations to ensure that the read write heads are properlyaligned on the track. As a result of receiving the position errorinformation, the servo controller generates a corresponding controlsignal to position the read write heads by positioning the voice coilmotor. The track identification information is also used during read andwrite operations so that a track may be properly identified.

[0005] Hard disk drive designers strive to provide higher capacitydrives that operate at a high signal to noise ratio and a lower biterror rate. To achieve higher capacities, the aerial density of the datastored on each side of the platter must be increased.

[0006] It can be appreciated that there is a need for detecting an opencircuit or any kind of fault in the write head. Such a fault wouldprevent data from being written to the medium and without such a faultindication, the fault would go unnoticed or undetected. Consequently, itis desirable to detect this fault operation. Importantly, it necessaryto detect WDI to low open head, a short cross, which is a cross of the Xand Y, and short to ground which is when the head is short to ground.The fault, if undetected, could result in loss of data.

SUMMARY OF THE INVENTION

[0007] The present invention detects fault conditions during operationof the head for example, during read write operations by a write unsafedetector (WUS). The present invention uses advantageously the inductiveproperty of the head which cause a “kickback” when the current isswitched through the head. This kickback causes the voltage on one sideof the magnetic head to rise above the normal operating value. Thepresent invention recognizes that this kickback pulse would not bepresent if the head were open. By detecting the presence of this pulseduring each half of the write cycle, a write unsafe circuit candetermine if the head is in a normal operation or has opened.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 illustrates a WUS detector of the present invention;

[0009]FIG. 2 illustrates a WUS detector of the present invention;

[0010]FIG. 3 illustrates a wave form diagram of the present invention;

[0011]FIG. 4 illustrates a wave form diagram of the present invention;

[0012]FIG. 5 illustrates a top view of a system of the presentinvention; and

[0013]FIG. 6 illustrates a side view of the system of the presentinvention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0014] The following invention is described with reference to figures inwhich similar or the same numbers represent the same or similarelements. While the invention is described in terms for achieving theinvention's objectives, it can be appreciated by those skilled in theart that variations may be accomplished in view of these teachingswithout deviation from the spirit or scope of the invention.

[0015]FIGS. 5 and 6 show a side and top view, respectively, of the diskdrive system designated by the general reference 1100 within anenclosure 1110. The disk drive system 1100 includes a plurality ofstacked magnetic recording disks 1112 mounted to a spindle 1114. Thedisks 1112 may be conventional particulate or thin film recording diskor, in other embodiments, they may be liquid-bearing disks. The spindle1114 is attached to a spindle motor 1116 which rotates the spindle 1114and disks 1112. A chassis 1120 is connected to the enclosure 1110,providing stable mechanical support for the disk drive system. Thespindle motor 1116 and the actuator shaft 1130 are attached to thechassis 1120. A hub assembly 1132 rotates about the actuator shaft 1130and supports a plurality of actuator arms 1134. The stack of actuatorarms 1134 is sometimes referred to as a “comb.” A rotary voice coilmotor 1140 is attached to chassis 1120 and to a rear portion of theactuator arms 1134.

[0016] A plurality of head suspension assemblies 1150 are attached tothe actuator arms 1134. A plurality of inductive transducer heads 1152are attached respectively to the suspension assemblies 1150, each head1152 including at least one inductive write element. In additionthereto, each head 1152 may also include an inductive read element or aMR (magneto-resistive) read element. The heads 1152 are positionedproximate to the disks 1112 by the suspension assemblies 1150 so thatduring operation, the heads are in electromagnetic communication withthe disks 1112. The rotary voice coil motor 1140 rotates the actuatorarms 1134 about the actuator shaft 1130 in order to move the headsuspension assemblies 1150 to the desired radial position on disks 1112.

[0017] A controller unit 1160 provides overall control to the disk drivesystem 1100, including rotation control of the disks 1112 and positioncontrol of the heads 1152. The controller unit 1160 typically includes(not shown) a central processing unit (CPU), a memory unit and otherdigital circuitry, although it should be apparent that these aspectscould also be enabled as hardware logic by one skilled in the computerarts. Controller unit 1160 is connected to the actuator control/driveunit 1166 which is in turn connected to the rotary voice coil motor1140. A host system 1180, typically a computer system or personalcomputer (PC), is connected to the controller unit 1160. The host system1180 may send digital data to the controller unit 1160 to be stored onthe disks, or it may request that digital data at a specified locationbe read from the disks 1112 and sent back to the host system 1180. Aread/write channel 1190 is coupled to receive and condition read andwrite signals generated by the controller unit 1160 and communicate themto an arm electronics (AE) unit shown generally at 1192 through acut-away portion of the voice coil motor 1140. The AE unit 1192 includesa printed circuit board 1193, or a flexible carrier, mounted on theactuator arms 1134 or in close proximity thereto, and an AE module 1194mounted on the printed circuit board 1193 or carrier that comprisescircuitry preferably implemented in an integrated circuit (IC) chipincluding read drivers, write drivers, and associated control circuitry.The AE module 1194 is coupled via connections in the printed circuitboard to the read/write channel 1190 and also to each read head and eachwrite head in the plurality of heads 1152. The AE module 1194 includesthe WUS detector of the present invention.

[0018] Turning now to FIG. 3, FIG. 3 illustrates the output signal ofpre-amplifier 202. The output signal of pre-amplifier 202 is adifferential signal and indicated in FIG. 2 as signal H_(X) and thesignal H_(Y). A comparator 204 is connected to the output ofpre-amplifier 202 to compare the signal H_(X) with a threshold voltageV_(TH). The V_(TH) is normally set at 5 volts but other voltages couldbe used. The 5 volt threshold voltage V_(TH) is approximately half ofthe maximum kickback voltage and consequently can be used to provide agood indication of the kickback voltage. The output of comparator 204 issignal SW2 which indicates when the signal H_(X) exceeds the thresholdvoltage V_(TH) when signal to provide an indication of the presence ofthe kickback voltage. In the absence of the kickback voltage, indicatinga fault or a combination of, namely WDI too low, an open head, a shortcross, or a short to ground, of the write head, signal SW2 is a zero.Likewise, under the presence of the kickback voltage, the signal SW2 isa logical one. A similar circuit is found with respect to the otheroutput of the differential pre-amplifier 202. Another comparator 206receives the signal H_(Y) as the output of differential pre-amplifier202. Additionally, input to the comparator 206 is a threshold voltageV_(TH) which as described before is approximately 5 volts, and thisvalue is again chosen in that the kickback voltage with respect to thewide differential voltage. Again, when the kickback voltage hasoccurred, the kickback voltage normally will exceed the thresholdvoltage V_(TH) and the comparator 206 will output a logical one assignal SW1 to indicate that the kickback signal is present. In theabsence of the kickback's signal, the threshold voltage is not receivedand signal SW1 is a logical zero to indicate a fault.

[0019] Turning now to FIG. 1, FIG. 1 illustrates two switches, switch102 and switch 104 being connected to voltage V_(CC). The switch 104 isactivated by signal SW1 and consequently is connected to comparator 204.When signal SW2 is a logical one, switch 102 closes allowing current toflow to capacitor 106; this raises the voltage on capacitor 106, raisingvoltage V_(TH). When switches 104 and 106 are open, voltage V_(DET)falls as a result of current flow out of capacitor 106. Likewise, switch104 is controlled by signal SW1 and correspondingly is connected tocomparator 206. When comparator 206 outputs a logical one as signal SW1,switch 104 closes again allowing a voltage to form on capacitor 106 bythe current flowing into capacitor 106. The voltage on capacitor 106 isdesignated as voltage V_(DET). A current generator 108 is connected inparallel with capacitor 106. Both current generator 108 and capacitor106 are connected to switch 104 and switch 102. Switch 102 and switch104 are connected to comparator 110 to provide a fault signal (FLT) toindicate that there has been a WDI fault, an open head fault, a shortcross fault. Additionally, input to comparator 110 is a thresholdvoltage equal to V_(FLT-TH).

[0020]FIG. 4 illustrates a wave form showing the voltage V_(DET) as afunction of time. The voltage V_(DET) at position 302 is low. Atposition 302 a kickback voltage has been received and either switch 104or switch 102 closes causing V_(DET) to rise to position 304. Atposition 304, the kickback voltage reaches its peak as well as voltageV_(DET) and begins to decrease until position 306. The kickback voltageis below the threshold voltage and both switch 102 and switch 104 closesat position 306. The voltage V_(DET) decreases as a result of currentflowing from the capacitor to the current generator 108.

[0021]FIG. 4 illustrates the WDI voltage for both H_(X) and H_(Y).Additionally, it shows the corresponding head voltage.

[0022] The switch 102 and switch 104 when connected to V_(CC) providecurrent to capacitor 106 to increase the voltage on capacitor, whenswitch 102 and 104 are both disconnected from capacitor 106. The voltageor capacitor 106 drop as a result of current flowing from capacitor 106to current source 108.

[0023] A voltage V_(DET) decreases at position 308 as a result ofcurrent flowing from the capacitor to the current generator 108 andfinally go below voltage V_(TH) 2 when no SW1 and SW2 are generated.Then, FLT signal is generated by comparator 101.

1. An unsafe detection circuit for detecting an absence of a kickbacksignal; comprising: an input circuit for inputting a kickback signal; acircuit for detecting the presence or absence of said kickback signal;and a fault detection circuit to respond to said presence or absence ofsaid kickback signal to provide an indication of a fault.
 2. An unsafedetection circuit as in claim 1 wherein said current for detecting saidkickback signal includes a threshold circuit.
 3. An unsafe detectioncircuit as in claim 1 wherein said circuit for detecting said kickbacksignal includes a capacitor.
 4. An unsafe detection circuit as in claim1 wherein said fault detector includes a capacitor to hold said nonfaultsignal.
 5. An unsafe detection circuit as in claim 4 wherein said faultdetector includes switch response to said kickback signal to charge saidcapacitor.
 6. An unsafe detection circuit as in claim 1 wherein saidkickback signal includes a differential signal.
 7. An unsafe detectioncircuit as in claim 1 wherein said input circuit includes apre-amplifier.
 8. An unsafe detection circuit for detecting a kickbacksignal; comprising: an input circuit for inputting a kickback signal; acircuit for detecting the presence or absence of said kickback signal;and a fault detection circuit to respond to said presence or absence ofsaid kickback signal to provide an indication of a fault